These are the most frequently used words in another edition of this book.
architecture
argument
arithmetic
array
assignment
attribute
behaviour
between
bit
boolean
called
case
chapter
character
circuit
ck
clock
comparison
complex
component
condition
constant
conversion
data
declaration
defined
design
different
downto
element
end
entity
example
figure
first
following
form
function
give
however
ieee
input
integer
language
length
library
logic
loop
means
model
must
name
natural
number
operations
operators
output
package
parameters
part
port
possible
procedure
process
range
read
register
reset
result
return
section
set
shift
should
sign
signal
signed
simulation
since
size
standard
state
statement
std_logic
std_logic_vector
string
synthesis
synthesiser
template
test
time
two
type
unsigned
use
used
value
variable
vhdl
wait