- Paperback: 304 pages
- Publisher: Morgan Kaufmann (18 Jan 2008)
- Language English
- ISBN-10: 0123742498
- ISBN-13: 978-0123742490
- Product Dimensions: 23.5 x 19.3 x 1.5 cm
- Amazon Bestsellers Rank: 1,256,559 in Books (See Top 100 in Books)
VHDL 2008: Just the New Stuff (Systems on Silicon)
and over one million other books are available for Amazon Kindle .
Learn more
| |||||||||||||||
Did you know you can trade in your old books for an Amazon.co.uk Gift Card to spend on the things you want? Plus, get an extra £5 Gift Certificate when you trade in books worth £10 or more before June 30, 2012. Visit the Books Trade-In Store for more details. |
Product details |
More About the Author
Product Description
Product Description
"VHDL-2008: Just the New Stuff", as its title says, introduces the new features added to the latest revision of the IEEE standard for the VHDL hardware description language. Written by the Chair and Technical Editor of the IEEE working group, the book is an authoritative guide to how the new features work and how to use them to improve design productivity. It will be invaluable for early adopters of the new language version, for tool implementers, and for those just curious about where VHDL is headed. It is the first in the market - describing the new features of VHDL 2008 - just the new features, so existing users and implementers can focus on what's new. It helps readers to learn the new features soon, rather than waiting for new editions of complete VHDL reference books. It is authoritative, written by experts in the area. Ii is written in tutorial style, making it more accessible than the "VHDL Standard Language Reference Manual".
About the Author
Peter J. Ashenden received his B.Sc.(Hons) and Ph.D. from the University of Adelaide, Australia. He was previously a senior lecturer in computer science and is now a Visiting Research Fellow at the University of Adelaide. His research interests are computer organization and electronic design automation. Dr. Ashenden is also an independent consultant specializing in electronic design automation (EDA). He is actively involved in IEEE working groups developing VHDL standards, is the author of The Designer's Guide to VHDL and The Student's Guide to VHDL and co-editor of the Morgan Kaufmann series, Systems on Silicon. He is a senior member of the IEEE and a member of the ACM.
Inside This Book
(Learn More)
Tag this product(What's this?)Think of a tag as a keyword or label you consider is strongly related to this product.
Tags will help all customers organise and find favourite items. |
What Other Items Do Customers Buy After Viewing This Item?
Customer Reviews
There are no customer reviews yet on Amazon.co.uk.
5 star
4 star
3 star
2 star
1 star
Most Helpful Customer Reviews on Amazon.com (beta)
Amazon.com:
2 reviews
1 of 1 people found the following review helpful
Great intro
28 April 2010
Format:Paperback|Amazon Verified Purchase
As the title says, this presents only the deltas from the previous version of the spec. If you're not already reasonably conversant with VHDL, this won't do a thing for you. But, if you've used VHDL long enough to be utterly maddened by some of its shortcomings, get this one. You're in for some happy surprises.
The two biggest changes have to do with generics and with assertions. Since day one, logic designers have treated strongly-typed VHDL as an untyped language. We've had to cast everything to bitvectors, like a PL/I programmer who uses unspec for everything, because of inflexible typing. A FIFO, for example, that handled one data type could never be reused with a different type. You'd have rewrite the entire FIFO, identical in every way, except for the data type. Yuk - better to cast everything to std_logic_vector, reuse the component, and adopt the old C-language slogan: "strong typing is for weak memories." Generic types, more like C++ templates, get past that. Generic subprograms increase reusability, too. If you're new to the concept, it's like passing a function as parameter, but at compile time. In the world VHDL addresses, compile-time binding is just fine.
Much has been made of SystemVerilog assertions - and with good reason. They add a huge level of expressiveness to the verification engineer's task, and represented a real advance over what VHDL had. The gap closes with VHDL's integrated PSL. I haven't done a point by point comparison, but SV assertions and PSL appear to have closely comparable feature sets. That includes Verilog's scope-busting ability to reach internal signals deep down in the structure hierarchy, but PSL allows up-level references, too.
VHDL 2008 also includes minor features that scratch many itches from the previous standards: ability to use std_logic values as "if" tests without casting to boolean, conditional assignments in sequential blocks, bitwise reduction operators, and fixes to other niggling annoyances that people have been coding around for years.
The one thing conspicuous by its absence is mention of what's in the synthesizable subset. Using advanced features in testbenches is nice. But, if you can't put them in the payload logic, they tend to create impedance mismatch where the application plugs into the test harness. Also, one of VHDL's big advantages has been its formally standardized synthesizable subset. That meant you could code for one tool suite and have some assurance that your work would port to other tools, too. Without that kind of contract for reusability, the new features (especially richer generics) will never live up to their promise.
This book is just a stopgap, and will become obsolete once complete VHDL references include the new features. Those books aren't out yet, however, and this is. For now, I recommend this highly to anyone who uses or develops VHDL tools.
-- wiredweird
The two biggest changes have to do with generics and with assertions. Since day one, logic designers have treated strongly-typed VHDL as an untyped language. We've had to cast everything to bitvectors, like a PL/I programmer who uses unspec for everything, because of inflexible typing. A FIFO, for example, that handled one data type could never be reused with a different type. You'd have rewrite the entire FIFO, identical in every way, except for the data type. Yuk - better to cast everything to std_logic_vector, reuse the component, and adopt the old C-language slogan: "strong typing is for weak memories." Generic types, more like C++ templates, get past that. Generic subprograms increase reusability, too. If you're new to the concept, it's like passing a function as parameter, but at compile time. In the world VHDL addresses, compile-time binding is just fine.
Much has been made of SystemVerilog assertions - and with good reason. They add a huge level of expressiveness to the verification engineer's task, and represented a real advance over what VHDL had. The gap closes with VHDL's integrated PSL. I haven't done a point by point comparison, but SV assertions and PSL appear to have closely comparable feature sets. That includes Verilog's scope-busting ability to reach internal signals deep down in the structure hierarchy, but PSL allows up-level references, too.
VHDL 2008 also includes minor features that scratch many itches from the previous standards: ability to use std_logic values as "if" tests without casting to boolean, conditional assignments in sequential blocks, bitwise reduction operators, and fixes to other niggling annoyances that people have been coding around for years.
The one thing conspicuous by its absence is mention of what's in the synthesizable subset. Using advanced features in testbenches is nice. But, if you can't put them in the payload logic, they tend to create impedance mismatch where the application plugs into the test harness. Also, one of VHDL's big advantages has been its formally standardized synthesizable subset. That meant you could code for one tool suite and have some assurance that your work would port to other tools, too. Without that kind of contract for reusability, the new features (especially richer generics) will never live up to their promise.
This book is just a stopgap, and will become obsolete once complete VHDL references include the new features. Those books aren't out yet, however, and this is. For now, I recommend this highly to anyone who uses or develops VHDL tools.
-- wiredweird
2 of 3 people found the following review helpful
understandable discussion of enhancements
19 Jan 2008
Format:Paperback
Well, you had better be well acquainted with the earlier VHDL standard. What this book does is focus on the deltas. The changes or improvements that have been promulgated for release in the VHDL 2008. In straightforward language, the text explains how to use the new features. The basic syntax of VHDL is still unchanged, as you'd expect.
But now there are enhancements. Like in the IP encryption. To let IP vendors/owners more securely protect their code when it is downloaded to customers' machines. The discussion quickly goes over the ideas behind public key encryption and symmetric ciphers. However, all you have to know is the broad outlines of these. No indepth mathematical reasoning is necessitated. The 2008 standard comes with many parameters for IP encryption that can be tweaked by the vendor.
But now there are enhancements. Like in the IP encryption. To let IP vendors/owners more securely protect their code when it is downloaded to customers' machines. The discussion quickly goes over the ideas behind public key encryption and symmetric ciphers. However, all you have to know is the broad outlines of these. No indepth mathematical reasoning is necessitated. The 2008 standard comes with many parameters for IP encryption that can be tweaked by the vendor.
Were these reviews helpful?
Let us know
Listmania!
Look for similar items by category
Look for similar items by subject
Feedback
- Would you like to update product info or give feedback on images?
- I am the Author, and I want to comment on my book.
- I am the Publisher, and I want to comment on this book.
|
