In this book, Comer specialises to the design of network processor chips. He explains why these have arisen in importance in recent years, due to ever increasing network traffic, and the need to process this as quickly as possible.
The chips described in the text are RISC designs, and fall between CISCs and ASICs, in terms of cost and other metrics. ASIC designs for network processing tend to take too long (2 years!) to design. The RISC network processors can be as fast as ASICs. They have a minimal set of instructions, that are capable of handling various protocols very quickly.
The text covers many aspects of the design. Like scaling issues of bandwidth. This can be increased, for accessing memory that is off-chip. But a cost is the increased interconnect area needed on the processor chip. The text also mentions the ironic point that unlike general purpose CPUs, increasing the cache has little benefit here. A cache is best suited when given data is repeatedly looked up by the CPU. But a network processor often just analyses a packet and pushes it out. The heavier the network traffic, the greater the chance that packets come and go everywhere on the network. So even less use for a cache.
Comer gives considerable detail in the case study of the Intel network processor. Useful for you to glean how Intel implemented many of the ideas in the text.
All the chapters are reasonably short. Each could be envisaged as mapping to one or two lectures. Something to consider if you are a lecturer needing a text on this subject.